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ltc3786 1 3786fa typical a pplica t ion fea t ures descrip t ion low i q synchronous boost controller the ltc ? 3786 is a high performance synchronous boost converter controller that drives all n-channel power mosfets. synchronous rectification increases efficiency, reduces power losses and eases thermal requirements, allowing the ltc3786 to be used in high power boost applications. a 4.5v to 38v input supply range encompasses a wide range of system architectures and battery chemistries. when biased from the output of the boost converter or another auxiliary supply, the ltc3786 can operate from an input supply as low as 2.5v after start-up. the 55a no-load quiescent current extends operating run time in battery-powered systems. the operating frequency can be set for a 50khz to 900khz range or synchronized to an external clock using the internal pll. the ltc3786 also features a precision 1.2v reference and a power good output indicator. the ss pin ramps the output voltage during start-up. the pllin/mode pin selects among burst mode ? operation, pulse-skipping mode or continuous inductor current mode at light loads. 12v to 24v/5a synchronous boost converter a pplica t ions n synchronous operation for highest efficiency and reduced heat dissipation n wide v in range: 4.5v to 38v (40v abs max) and operates down to 2.5v after start-up n output voltages up to 60v n 1% 1.2v reference voltage n r sense or inductor dcr current sensing n 100% duty cycle capability for synchronous mosfet n low quiescent current: 55a n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n adjustable output voltage soft-start n power good output voltage monitor n low shutdown current i q : <8a n internal 5.4v ldo for gate drive supply n thermally enhanced 16-pin 3mm 3mm qfn and msop packages n industrial and automotive power supplies n automotive start-stop systems n medical devices n high voltage battery-powered systems l , lt, ltc, ltm, burst mode, opti-loop, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u. s. patents, including 5408150, 5481178, 5705919, 5929620, 6177787, 6498466, 6580258, 6611131. sense + vbias sense ? tg 0.1f 220pf ltc3786 0.1f 15nf 220f 220f 3786 ta01a v out 24v 5a 4.7f v in 4.5v to 24v 4m 3.3h boost sw bg gnd intv cc vfb ith ss 12.1k 8.66k 232k freq run pllin/mode pgood efficiency and power loss vs load current output current (a) 0.01 0.001 0.0001 0.00001 40 efficiency (%) power loss (mw) 50 60 70 80 0.1 1 10 3786 ta01b 30 20 10 0 90 100 10 100 1000 1 0.1 10000 v in = 12v v out = 24v burst mode operation figure 8 circuit burst efficiency burst loss
ltc3786 2 3786fa a bsolu t e maxi m u m r a t ings vbias ........................................................ C0 .3v to 40v boost ........................................................ C 0.3v to 71v sw ............................................................. C0 .3v to 65v run ............................................................. C 0.3v to 8v ma ximum current sourced into pin fro m source >8v .............................................. 10 0a pgood, pllin/mode .................................. C0 .3v to 6v intv cc , (boost C sw) ............................... C0 .3v to 6v (notes 1, 3) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3786emse#pbf ltc3786emse#trpbf 3786 16-lead plastic msop C40c to 125c ltc3786imse#pbf ltc3786imse#trpbf 3786 16-lead plastic msop C40c to 125c ltc3786eud#pbf ltc3786eud#trpbf lfxw 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc3786iud#pbf ltc3786iud#trpbf lfxw 16-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 1 2 3 4 5 6 7 8 vfb sense + sense ? ith ss pllin/mode freq run 16 15 14 13 12 11 10 9 pgood sw tg boost vbias intv cc bg gnd top view 17 gnd mse package 16-lead plastic msop t jmax = 125c, ja = 40c/w, jc = 10c/w exposed pad (pin 17) is gnd, must be soldered to pcb 16 15 14 13 5 6 7 8 top view 17 gnd ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1sw pgood vfb sense + bg gnd run freq tg boost vbias intv cc sense ? ith ss pllin/ mode t jmax = 125c, ja = 68c/w, jc = 4.2c/w exposed pad (pin 17) is gnd, must be soldered to pcb p in c on f igura t ion sense + , sense C ........................................ C0 .3v to 40v sense + C sense C ..................................... C0 .3v to 0.3v ss, ith, freq, vfb............................... C0.3v to intv cc operating junction temperature range ... C4 0c to 125c storage temperature range .................. C 65c to 125c lead temperature (soldering, 10 sec) ms e package only ............................................ 3 00c
ltc3786 3 3786fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, unless otherwise noted (note 2). symbol parameter conditions min typ max units main control loop vbias chip bias voltage operating range 4.5 38 v v fb regulated feedback voltage i th = 1.2v (note 4) l 1.188 1.200 1.212 v i fb feedback current (note 4) 5 50 na v reflnreg reference line voltage regulation v bias = 6v to 38v 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v measured in servo loop; ?i th voltage = 1.2v to 2v l l 0.01 C0.01 0.1 C0.1 % % g m error amplifier transconductance i th = 1.2v 2 mmho i q input dc supply current pulse-skipping or forced continuous mode sleep mode shutdown (note 5) run = 5v; v fb = 1.25v (no load) run = 5v; v fb = 1.25v (no load) run = 0v 0.8 55 8 80 20 ma a a uvlo intv cc undervoltage lockout thresholds v intvcc ramping up v intvcc ramping down l l 3.6 4.1 3.8 4.3 v v v run run pin on threshold v run rising l 1.18 1.28 1.38 v v runhys run pin hysteresis 100 mv i runhys run pin hysteresis current v run > 1.28v 4.5 a i run run pin current v run < 1.28v 0.5 a i ss soft-start charge current v ss = 0v 7 10 13 a v sense(max) maximum current sense threshold v fb = 1.1v l 68 75 82 mv v sense(cm) sense pins common mode range (boost converter input supply voltage v in ) 2.5 38 v i sense + sense + pin current v fb = 1.1v 200 300 a i sense C sense C pin current v fb = 1.1v 1 a t r(tg) top gate rise time c load = 3300pf (note 6) 20 ns t f(tg) top gate fall time c load = 3300pf (note 6) 20 ns t r(bg) bottom gate rise time c load = 3300pf (note 6) 20 ns t f(bg) bottom gate fall time c load = 3300pf (note 6) 20 ns r up(tg) top gate pull-up resistance 1.2 r dn(tg) top gate pull-down resistance 1.2 r up(bg) bottom gate pull-up resistance 1.2 r dn(bg) bottom gate pull-down resistance 1.2 t d(tg/bg) top gate off to bottom gate on switch-on delay time c load = 3300pf (each driver) 80 ns t d(bg/tg) bottom gate off to top gate on switch-on delay time c load = 3300pf (each driver) 80 ns df maxbg maximum bg duty factor 96 % t on(min) minimum bg on-time (note 7) 110 ns
ltc3786 4 3786fa e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3786 is tested under pulsed load conditions such that t j t a . the ltc3786e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3786i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) where ja = 68c for the qfn package and ja = 40c for the msop package. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v bias = 12v, unless otherwise noted (note 2). symbol parameter conditions min typ max units intv cc linear regulator v intvcc(vin) internal v cc voltage 6v < vbias < 38v 5.2 5.4 5.6 v v ldo int intv cc load regulation i cc = 0ma to 50ma 0.5 2 % oscillator and phase-locked loop f prog programmable frequency r freq = 25k r freq = 60k r freq = 100k 335 105 400 760 465 khz khz khz f low lowest fixed frequency v freq = 0v 320 350 380 khz f high highest fixed frequency v freq = intv cc 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pgood output v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative hysteresis v fb ramping positive hysteresis C12 8 C10 2.5 10 2.5 C8 12 % % % % t pgood(delay) pgood delay pgood going high to low 25 s boost charge pump i boost boost charge pump available output current v sw = 12v; v boost C v sw = 4.5v; freq = 0v, forced continuous or pulse-skipping mode 85 a note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc3786 is tested in a feedback loop that servos v fb to the output of the error amplifier while maintaining i th at the midpoint of the current limit range. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: see minimum on-time considerations in the applications information section.
ltc3786 5 3786fa typical p er f or m ance c harac t eris t ics efficiency vs input voltage load step forced continuous mode load step burst mode operation load step pulse-skipping mode inductor current at light load soft start-up efficiency and power loss vs output current efficiency and power loss vs output current output current (a) 0.01 40 efficiency (%) power loss (mw) 50 60 70 80 0.1 1 10 3786 g01 30 20 10 0 90 100 10 100 1000 1 0.1 10000 ccm efficiency cmm loss burst efficiency burst loss pulse-skipping efficiency pulse-skipping loss v in = 12v v out = 24v figure 8 circuit output current (a) 0.01 0.001 0.0001 0.00001 40 efficiency (%) power loss (mw) 50 60 70 80 0.1 1 10 3786 g02 30 20 10 0 90 100 10 100 1000 1 0.1 10000 v in = 12v v out = 24v burst mode operation figure 8 circuit burst efficiency burst loss input voltage (v) 0 98 99 100 20 3786 g03 97 96 5 10 15 25 95 94 93 efficiency (%) v out = 12v v out = 24v i load = 2a figure 8 circuit load step 2a/div v out 500mv/div 200s/div 3786 g04 v in = 12v v out = 24v load step from 200ma to 2.5a figure 8 circuit inductor current 5a/div load step 2a/div v out 500mv/div 200s/div 3786 g05 v in = 12v v out = 24v load step from 200ma to 2.5a figure 8 circuit inductor current 5a/div load step 2a/div v out 500mv/div 200s/div 3786 g06 v in = 12v v out = 24v load step from 200ma to 2.5a figure 8 circuit inductor current 5a/div burst mode operation 5a/div pulse- skipping mode 5s/div 3786 g07 v in = 12v v out = 24v i load = 200a figure 8 circuit forced continuous mode v out 5v/div 0v 20ms/div 3786 g08 v in = 12v v out = 24v figure 8 circuit
ltc3786 6 3786fa typical p er f or m ance c harac t eris t ics shutdown current vs input voltage quiescent current vs temperature shutdown (run) threshold vs temperature undervoltage lockout threshold vs temperature intv cc line regulation intv cc line regulation regulated feedback voltage vs temperature soft-start pull-up current vs temperature shutdown current vs temperature temperature (c) ?45 regulated feedback voltage (v) 1.209 30 3786 g09 1.200 1.194 ?20 5 55 1.191 1.188 1.212 1.206 1.203 1.197 80 105 130 temperature (c) ?45 soft-start current (a) 10.5 30 3786 g10 ?20 5 55 9.0 11.0 10.0 9.5 80 105 130 ?45 30 ?20 5 55 80 105 130 temperature (c) shutdown current (a) 7.0 9.5 10.0 10.5 11.0 6.0 8.5 6.5 9.0 5.5 5.0 8.0 7.5 3786 g11 v in = 12v 0 15 5 10 20 25 30 35 40 input voltage (v) shutdown current (a) 10 20 5 0 15 3786 g12 temperature (c) ?45 run pin voltage (v) 30 3786 g14 1.25 1.15 ?20 5 55 1.10 1.40 1.35 1.30 1.20 80 105 130 run falling run rising ?45 30 ?20 5 55 80 105 130 temperature (c) intv cc voltage (v) 3.6 4.1 4.2 4.3 4.4 3.9 3.5 4.0 3.4 3.8 3.7 3786 g15 intv cc rising intv cc falling temperature (c) ?45 quiescent current (a) 60 70 80 30 80 3786 g13 50 40 ?20 5 55 105 130 30 20 v in = 12v v fb = 1.25v input voltage (v) 0 4.5 intv cc voltage (v) 4.6 4.8 4.9 5.0 5.5 5.2 10 20 25 3786 g16 4.7 5.3 5.4 5.1 5 15 30 35 40 no load input voltage (v) 4.5 4.5 intv cc voltage (v) 4.7 4.9 5.1 4.75 5.0 5.25 5.5 3786 g17 5.75 5.3 5.5 4.6 4.8 5.0 5.2 5.4 6.0 no load
ltc3786 7 3786fa typical p er f or m ance c harac t eris t ics oscillator frequency vs input voltage maximum current sense threshold vs i th voltage sense pin input current vs temperature sense pin input current vs i th voltage sense pin input current vs v sense voltage maximum current sense threshold vs duty cycle intv cc vs load current intv cc vs load current oscillator frequency vs temperature temperature (c) ?45 300 frequency (khz) 350 600 450 5 55 80 500 550 400 ?20 30 105 130 3786 g20 freq = gnd freq = intv cc 15 5 10 20 25 30 35 40 input voltage (v) oscillator frequency (khz) 344 354 356 358 360 350 342 352 340 348 346 3786 g21 freq = gnd temperature (c) ?45 sense current (a) 5 55 80 0 80 40 160 200 240 120 20 100 60 180 220 260 140 ?20 30 105 130 3786 g23 sense + pin sense ? pin v sense = 12v i th voltage (v) 0 maximum current sense voltage (mv) 80 120 100 0.6 1.0 3786 g22 40 0 0.2 0.4 0.8 1.2 1.4 ?40 60 20 ?20 ?60 pulse-skipping mode forced continuous mode burst mode operation i th voltage (v) 0 sense current (a) 1 2 2.5 0 80 40 160 200 240 120 20 100 60 180 220 260 140 0.5 1.5 3 3786 g24 sense + pin sense ? pin v sense = 12v v sense common mode voltage (v) 2.5 sense current (a) 17.5 27.5 32.5 0 80 40 160 200 240 120 20 100 60 180 220 260 140 7.5 12.5 22.5 37.5 3786 g25 sense + pin sense ? pin duty cycle (%) 0 maximum current sense voltage (mv) 80 100 70 60 40 20 40 10 90 30 50 80 60 100 20 0 120 3786 g26 load current (ma) 0 5.15 intv cc voltage (v) 5.20 5.30 5.35 120 40 5.50 3786 g18 5.25 20 60 100 160140 80 180 5.40 5.45 v in = 12v load current (ma) 0 4.0 intv cc voltage (v) 4.2 4.4 4.6 4.8 5.2 10 20 30 40 3786 g19 50 60 5.0 v in = 5v
ltc3786 8 3786fa typical p er f or m ance c harac t eris t ics charge pump charging current vs operating frequency charge pump charging current vs switch voltage p in func t ions (msop/qfn) vfb (pin 1/pin 3): error amplifier feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider connected across the output. sense + (pin 2/pin 4): positive current sense comparator input. the (+) input to the current comparator is normally connected to the positive terminal of a current sense resis- tor. the current sense resistor is normally placed at the input of the boost controller in series with the inductor. this pin also supplies power to the current comparator. sense C (pin 3/pin 5): negative current sense comparator input. the (C) input to the current comparator is normally connected to the negative terminal of a current sense re- sistor connected in series with the inductor. the common mode voltage range on the sense + and sense C pins is 2.5v to 38v (40v abs max). ith (pin 4/pin 6): current control threshold and error amplifier compensation point. the voltage on this pin sets the current trip threshold. ss (pin 5/pin 7): output soft-start input. a capacitor to ground at this pin sets the ramp rate of the output voltage during start-up. pllin/mode (pin 6/pin 9): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, it will force the controller into forced continuous mode of operation and the phase-locked loop will force the rising bg signal to be synchronized with the rising edge of the external clock. when not synchronizing to an external clock, this input determines how the ltc3786 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C 1.3v selects pulse-skipping operation. this can be done by adding a 100k resistor between the pllin/ mode pin and intv cc . operating frequency (khz) 50 150 0 charge pump charging current (a) 20 10 40 30 60 50 80 70 250 350 450 550 650 3786 g27 750 110 100 90 ?45c 130c 25c v boost = 16.5v v sw = 12v switch voltage (v) 5 charge pump charging current (a) 80 100 120 20 30 3786 g28 60 40 10 15 25 35 40 20 0 freq = 0v freq = intv cc
ltc3786 9 3786fa p in func t ions (msop/qfn) freq (pin 7/pin 9): the frequency control pin for the internal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350khz. connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz. the frequency can be programmed from 50khz to 900khz by connecting a resistor from the freq pin to gnd. the resistor and an internal 20a source current create a voltage used by the internal oscillator to set the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. run (pin 8/pin 10): run control input. forcing this pin below 1.28v shuts down the controller. forcing this pin below 0.7v shuts down the entire ltc3786, reducing quiescent current to approximately 8a. an external resistor divider connected to v in can set the threshold for converter operation. once running, a 4.5a current is sourced from the run pin allowing the user to program hysteresis using the resistor values. gnd (pin 9, exposed pad pin 17/ pin 11, exposed pad pin 17): ground. connects to the source of the bottom (main) n-channel mosfet and the (C) terminal(s) of c in and c out . all small-signal components and compensa- tion components should also connect to this ground. the exposed pad must be soldered to the pcb for rated thermal performance. bg (pin 10/pin 12): bottom gate. connect to the gate of the main n-channel mosfet. intv cc (pin 11/pin 13): output of internal 5.4v ldo. power supply for control circuits and gate drivers. de - couple this pin to gnd with a minimum 4.7f low esr ceramic capacitor. vbias (pin 12/pin 14): main supply pin. it is normally tied to the input supply v in or to the output of the boost converter. a bypass capacitor should be tied between this pin and the gnd pin. the operating voltage range on this pin is 4.5v to 38v (40v abs max). boost (pin 13/pin 15): floating power supply for the synchronous mosfet. bypass to sw with a capacitor and supply with a schottky diode connected to intv cc . tg (pin 14/pin 16): top gate. connect to the gate of the synchronous nmos. sw (pin 15/pin 1): switch node. connect to the source of the synchronous top mosfet, the drain of the main bottom mosfet, and the inductor. pgood (pin 16/pin 2): power good indicator. open-drain logic output that is pulled to ground when the output volt- age is more than 10 % away from the regulated output voltage. to avoid false trips the output voltage must be outside of the range for 25s before this output is activated.
ltc3786 10 3786fa b lock diagra m switching logic and charge pump 3.8v vbias v in c in intv cc pllin/ mode pgood 1.32v 1.08v + ? ? ? + ? + ? + v fb 5.4v ldo vco pfd sw 0.425v sens lo boost tg c b c out v out d b bg intv cc vfb s r q ea 1.32v ss 1.2v r sense 10a shdn shdn 2.5v r c ss sens lo ith c c c ss c c2 0.7v 2.8v slope comp 2mv sense ? sense + sleep shdn clk run gnd intv cc freq l + ? 3786 bd 20a 100k sync det 0.5a/ 4.5a 11v + ? + ? + ? + ? + ? + ? ov icmp irev
ltc3786 11 3786fa o pera t ion (refer to the block diagram) main control loop the ltc3786 uses a constant-frequency, current mode step-up control architecture. during normal operation, the external bottom mosfet is turned on when the clock sets the rs latch, and is turned off when the main current comparator, icmp , resets the rs latch. the peak inductor current at which icmp trips and resets the latch is con- trolled by the voltage on the ith pin, which is the output of the error amplifier, ea. the error amplifier compares the output voltage feedback signal at the vfb pin, (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 1.200v reference voltage. in a boost converter, the required inductor current is determined by the load current, v in and v out . when the load current increases, it causes a slight decrease in vfb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current in each channel matches the new requirement based on the new load current. after the bottom mosfet is turned off each cycle, the top mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. the vbias ldo (low dropout linear regulator) supplies 5.4v from vbias to intv cc . shutdown and start-up (run and ss pins) the ltc3786 can be shut down using the run pin. pulling this pin below 1.28v shuts down the main control loop. pulling this pin below 0.7v disables the controller and most internal circuits, including the intv cc ldos. in this state, the ltc3786 draws only 8a of quiescent current. note: do not apply load while the chip is in shutdown. the output mosfet will be turned off during shutdown and the output load may cause excessive power dissipation in the body diode. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low imped- ance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resis- tor to a higher voltage (for example, v in ), as long as the maximum current into the run pin does not exceed 100a. an external resistor divider connected to v in can set the threshold for converter operation. once running, a 4.5a current is sourced from the run pin allowing the user to program hysteresis using the resistor values. the start-up of the controllers output voltage, v out , is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 1.2v internal reference, the ltc3786 regulates the vfb voltage to the ss pin voltage instead of the 1.2v reference. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to gnd. an internal 10a pull- up current charges this capacitor creating a voltage ramp on the ss pin. as the ss voltage rises linearly from 0v to 1.2v, the output voltage rises smoothly to its final value. light load current operationburst mode operation, pulse-skipping or continuous conduction (pllin/mode pin) the ltc3786 can be enabled to enter high efficiency burst mode operation, constant-frequency pulse-skipping mode or forced continuous conduction mode at low load cur - rents. to select burst mode operation, tie the pllin/mode pin to ground. to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when the controller is enabled for burst mode opera- tion, the minimum peak current in the inductor is set to approximately 30% of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the required current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith voltage drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the ith pin is then disconnected from the output of the ea and parked at 0.450v.
ltc3786 12 3786fa o pera t ion (refer to the block diagram) in sleep mode, much of the internal circuitry is turned off and the ltc3786 draws only 55a of quiescent current. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the bottom external mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse- current comparator (ir) turns off the top external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous current operation. in forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see the frequency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur - rent is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantages of lower output voltage ripple and less interference to audio circuitry, as it maintains constant-frequency operation independent of load current. when the pllin/mode pin is connected for pulse-skipping mode, the ltc3786 operates in pwm pulse-skipping mode at light loads. in this mode, constant-frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator icmp may remain tripped for several cycles and force the external bottom mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3786s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to gnd, tied to intv cc , or programmed through an external resistor. tying freq to gnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and gnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 5. a phase-locked loop (pll) is available on the ltc3786 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc3786s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of the external bottom mosfet to the rising edge of the synchronizing signal. the vco input voltage is prebiased to the operating fre- quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of bg. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency.
ltc3786 13 3786fa o pera t ion (refer to the block diagram) the typical capture range of the ltc3786s pll is from approximately 55khz to 1mhz, and is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). operation when v in > regulated v out when v in rises above the regulated v out voltage, the boost controller can behave differently depending on the mode, inductor current and v in voltage. in forced continuous mode, the loop keeps the top mosfet on continuously once v in rises above v out . the internal charge pump delivers current to the boost capacitor to maintain a sufficiently high tg voltage. (the amount of current the charge pump can deliver is characterized by two curves in the typical performance characteristics section.) in pulse-skipping mode, if v in is between 100% and 110% of the regulated v out voltage, tg turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. this threshold current is set to approximately 4% of the maximum ilim current. if the controller is programmed to burst mode operation under this same v in window, then tg remains off regardless of the inductor current. if v in rises above 110% of the regulated v out voltage in any mode, the controller turns on tg regardless of the inductor current. in burst mode operation, however, the internal charge pump turns off if the chip is asleep. with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient tg voltage needed to keep the top mosfet completely on. to prevent excessive power dissipation across the body diode of the top mosfet in this situa- tion, the chip can be switched over to forced continuous or pulse-skipping mode to enable the charge pump, or a schottky diode can also be placed in parallel to the top mosfet. power good the pgood pin is connected to an open-drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the vfb pin voltage is not within 10% of the 1.2v reference voltage. the pgood pin is also pulled low when the corresponding run pin is low (shut down). when the vfb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v (abs max). operation at low sense pin common mode voltage the current comparator in the ltc3786 is powered directly from the sense + pin. this enables the common mode voltage of sense + and sense C pins to operate as low as 2.5v, which is below the intv cc uvlo threshold. the figure on the first page shows a typical application when the controllers vbias is powered from v out while v in supply can go as low as 2.5v. if the voltage on sense + drops below 2.5v, the ss pin will be held low. when the sense + voltage returns to the normal operating range, the ss pin will be released, initiating a new soft-start cycle. boost supply refresh and internal charge pump the top mosfet driver is biased from the floating boot- strap capacitor, c b , which normally recharges during each cycle through an external diode when the bottom mosfet turns on. there are two considerations to keep the boost supply at the required bias level. during start-up, if the bottom mosfet is not turned on within 100s after uvlo goes low, the bottom mosfet will be forced to turn on for ~400ns. this forced refresh generates enough boost- sw voltage to allow the top mosfet to be fully enhanced instead of waiting for the initial few cycles to charge the bootstrap capacitor, c b . there is also an internal charge pump that keeps the required bias on boost. the charge pump always operates in both forced continuous mode and pulse-skipping mode. in burst mode operation, the charge pump is turned off during sleep and enabled when the chip wakes up. the internal charge pump can normally supply a charging current of 85a.
ltc3786 14 3786fa a pplica t ions i n f or m a t ion the typical application on the first page is a basic ltc3786 application circuit. ltc3786 can be configured to use either inductor dcr (dc resistance) sensing or a discrete sense resistor (r sense ) for current sensing. the choice between the two current sensing schemes is largely a design trade- off between cost, power consumption and accuracy. dcr sensing is becoming popular because it does not require current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the se- lection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. the common mode input voltage range of the current comparators is 2.5v to 38v. the current sense resistor is normally placed at the input of the boost controller in series with the inductor. the sense + pin also provides power to the current com- parator. it draws ~200a during normal operation. there is a small base current of less than 1a that flows into the sense C pin. the high impedance sense C input to the current comparators allows accurate dcr sensing. filter components mutual to the sense lines should be placed close to the ltc3786, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. sense resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) of 75mv. the current comparator threshold sets the peak of the inductor current, yielding a maximum average inductor current, i max , equal to the peak value v in to sense filter, next to the controller inductor or r sense 3786 f01 (optional) v in v out 3786 f02a tg sw bg ltc3786 intv cc boost sense + sense ? vbias sgnd tg sw bg inductor dcr l ltc3786 intv cc boost sense + sense ? r2c1 vbias v in v out place c1 near sense pins sgnd 3786 f02b (r1 || r2) ? c1 = l dcr r sense(eq) = dcr ? r2 r1 + r2 r1 (2b) using the inductor dcr to sense current (2a) using a resistor to sense current figure 2. two different methods of sensing current figure 1. sense lines placement with inductor or sense resistor
ltc3786 15 3786fa a pplica t ions i n f or m a t ion less half the peak-to-peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 when using the controller in low v in and very high voltage output applications, the maximum inductor current and correspondingly the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for boost regulators operating at greater than 50% duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak inductor current level depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3786 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor can be less than 1m for high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor could reduce the efficiency by a few percent compared to dcr sensing. if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature. consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c. a conservative value for the maximum inductor temperature (t l(max) ) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense C pins 1a current. the equivalent resistance r1|| r2 is scaled to the room temperature inductance and maximum dcr: r1|| r2 = l dcr at 20c ( ) ? c1 the sense resistor values are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1C r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at v in = 1/2 v out : p loss _ r1 = v out ? v in ( ) ? v in r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method.
ltc3786 16 3786fa a pplica t ions i n f or m a t ion inductor value calculation the operating frequency and inductor selection are in - terrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge and switching losses. also, at higher frequency, the duty cycle of body diode conduction is higher, which results in lower efficiency. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ?i l decreases with higher inductance or frequency and increases with higher v in : ? i l = v in f ? l 1C v in v out ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.3(i max ). the maximum ?i l occurs at v in = 1/2 v out . the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. once the value of l is known, an inductor with low dcr and low core losses should be selected. power mosfet selection two external power mosfets must be selected for the ltc3786: one n-channel mosfet for the bottom (main) switch, and one n-channel mosfet for the top (synchro- nous) switch. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5.4v. consequently, logic- level threshold mosfets must be used in most applica - tions. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode, the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out C v in v out synchronous switch duty cycle = v in v out if the maximum output current is i out(max) and each chan- nel takes one-half of the total output current, the mosfet power dissipations in each channel at maximum output current are given by: p main = v out C v in ( ) v out v in 2 ? i out(max) 2 ? 1 + ( ) ? r ds(on) + k ? v out 3 ? i out(max) v in ? r dr ? c miller ? f p sync = v in v out ? i out(max) 2 ? 1 + ( ) ? r ds(on) where is the temperature dependency of r ds(on) (approximately 1) is the effective driver resistance at the mosfets miller threshold voltage. the constant k, which
ltc3786 17 3786fa a pplica t ions i n f or m a t ion accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. both mosfets have i 2 r losses while the bottom n-channel equation includes an additional term for transition losses, which are highest at low input voltages. for high v in the high current efficiency generally improves with larger mosfets, while for low v in the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the bottom switch duty factor is low or dur - ing overvoltage when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. c in and c out selection the input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. the input capacitor, c in , volt- age rating should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of the c in is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter, the output has a discontinuous current, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choos- ing the right capacitor for a given output ripple voltage. the steady ripple voltage due to charging and discharging the bulk capacitance in a single phase boost converter is given by: v ripple = i out(max) ? v out C v in(min) ( ) c out ? v out ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: ?v esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings (i.e., os-con and poscap). setting output voltage the ltc3786 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in figure 3. the regulated output voltage is determined by: v out = 1.2v 1 + r b r a ? ? ? ? ? ? great care should be taken to route the vfb line away from noise sources, such as the inductor or the sw line. also, keep the vfb node as small as possible to avoid noise pickup. ltc3786 vfb v out r b r a 3786 f03 figure 3. setting output voltage
ltc3786 18 3786fa a pplica t ions i n f or m a t ion soft-start (ss pin) the start-up of the v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 1.2v reference, the ltc3786 regulates the vfb pin voltage to the voltage on the ss pin instead of 1.2v. soft-start is enabled by simply connecting a capacitor from the ss pin to ground, as shown in figure 4. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the ss pin. the ltc3786 will regulate the v fb pin (and hence, v out ) according to the voltage on the ss pin, allowing v out to rise smoothly from v in to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 1.2v 10a temperature, the ltc3786 intv cc current is limited to less than 20ma in the qfn package from a 40v supply: t j = 70c + (20ma)(40v)(68c/w) = 125c in an msop package, the intv cc current is limited to less than 34ma from a 40v supply: t j = 70c + (34ma)(40v)(40c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = intv cc ) at maximum vbias. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the block diagram is charged though external diode, d b , from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v out and the boost pin follows. with the topside mosfet on, the boost voltage is above the output voltage: v boost = v out + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . the external diode d b can be a schottky diode or silicon diode, but in either case it should have low leakage and fast recovery. pay close attention to the reverse leakage at high temperatures where it generally increases substantially. the topside mosfet driver includes an internal charge pump that delivers current to the bootstrap capacitor from the boost pin. this charge current maintains the bias voltage required to keep the top mosfet on continuously during dropout/overvoltage conditions. the schottky/ silicon diode selected for the topside driver should have a reverse leakage less than the available output current the charge pump can supply. curves displaying the available charge pump current under different operating conditions can be found in the typical performance characteristics section. ltc3786 ss c ss sgnd 3786 f04 figure 4. using the ss pin to program soft-start intv cc regulator the ltc3786 features an internal p-channel low dropout linear regulator (ldo) that supplies power at the intv cc pin from the vbias supply pin. intv cc powers the gate drivers and much of the ltc3786s internal circuitry. the vbias ldo regulates intv cc to 5.4v. it can supply at least 50ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc3786 to be exceeded. the power dissipation for the ic is equal to vbias ? i intvcc . the gate charge current is dependent on operating frequency, as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, at 70c ambient
ltc3786 19 3786fa a pplica t ions i n f or m a t ion a leaky diode d b in the boost converter can not only prevent the top mosfet from fully turning on but it can also completely discharge the bootstrap capacitor c b and create a current path from the input voltage to the boost pin to intv cc . this can cause intv cc to rise if the diode leakage exceeds the current consumption on intv cc . this is particularly a concern in burst mode operation where the load on intv cc can be very small. the external schottky or silicon diode should be carefully chosen such that intv cc never gets charged up much higher than its normal regulation voltage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on-chip (such as an intv cc short to ground), the overtemperature shutdown circuitry will shut down the ltc3786. when the junction temperature exceeds approximately 170c, the overtemperature circuitry disables the intv cc ldo, causing the intv cc supply to collapse and effectively shut down the entire ltc3786 chip. once the junction temperature drops back to approximately 155c, the intv cc ldo turns back on. long-term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. since the shutdown may occur at full load, beware that the load current wont result in high power dissipation in the body diodes of the top mosfet. in this case, pgood output may be used to turn the system load off. phase-locked loop and frequency synchronization the ltc3786 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter and a voltage-controlled oscillator (vco). this allows the turn-on of the bottom mosfet to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the phase detector is an edge-sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced continu - ously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, c lp , holds the voltage at the vco input. typically, the external clock (on pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.2v. note that the ltc3786 can only be synchronized to an external clock whose frequency is within range of the ltc3786s internal vco, which is nominally 55khz to 1mhz. this is guaranteed to be between 75khz and 850khz. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchro- nization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchro- nization. although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3786 f05 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure 5. relationship between oscillator frequency and resistor value at the freq pin
ltc3786 20 3786fa a pplica t ions i n f or m a t ion table 2 summarizes the different states in which the freq pin can be used. table 2 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor dc voltage 50khz to 900khz any of the above external clock phase locked to external clock minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3786 is capable of turning on the bottom mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit. in forced continuous mode, if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles but the output will continue to be regulated. more cycles will be skipped when v in increases. once v in rises above v out , the loop keeps the top mosfet continuously on. the minimum on-time for the ltc3786 is approximately 110ns. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the greatest improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in ltc3786 circuits: 1) ic vbias current, 2) intv cc regulator current, 3) i 2 r losses, 4) bottom mosfet transi- tion losses and 5) body diode conduction losses. 1. the vbias current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. vbias current typically results in a small (<0.1%) loss. 2. int v cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mos- fets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor, inductor and pc board traces and cause the efficiency to drop at high output currents. 4. transition losses apply only to the bottom mosfet(s), and be come significant only when operating at low input voltages. transition losses can be estimated from: transition loss = 1.7 ( ) v out 3 v in i max ? c rss ? f 5. body diode conduction losses are more significant at higher switching frequency. during the dead time, the loss in the top mosfets is i l ? v ds , where v ds is around 0.7v. at higher switching frequency, the dead time becomes a good percentage of switching cycle and causes the efficiency to drop. other hidden losses, such as copper trace and internal battery resistances, can account for an additional efficiency degradation in portable systems. it is very important to include these system-level losses during the design phase.
ltc3786 21 3786fa a pplica t ions i n f or m a t ion checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out shifts by an amount equal to ? i load(esr) , where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regula - tor to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti - loop ? compen - sation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in the figure 8 circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly to optimize transient response once the final pcb layout is complete and the particular output capacitor type and value have been determined. the output capacitors must be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet and load resistor directly across the output capacitor and driving the gate with an appropriate pulse generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus, a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in = 12v(nominal), v in = 22v (max), v out = 24v, i out(max) = 4a, v sense(max) = 75mv and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. tie the mode/pllin pin to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: ? i l = v in f ? l 1C v in v out ? ? ? ? ? ? the largest ripple happens when v in = 1/2v out = 12v, where the average maximum inductor is i max = i out(max) ? (v out /v in ) = 8a. a 6.8h inductor will produce a 31% ripple current. the peak inductor current will be the maxi- mum dc value plus one-half the ripple current, or 9.25a.
ltc3786 22 3786fa a pplica t ions i n f or m a t ion the r sense resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: r sense 75mv 9.25a = 0.008 ? choosing 1% resistors: r a = 5k and r b = 95.3k yields an output voltage of 24.072v. the power dissipation on the topside mosfet in each chan- nel can be easily estimated. choosing a vishay si7848bdp mosfet results in: r ds(on) = 0.012, c miller = 150pf. at maximum input voltage with t(estimated) = 50c: p main = 24v C 12v ( ) 24v 12v ( ) 2 ? 4a ( ) 2 ? 1 + 0.005 ( ) 50 c C 25 c ( ) ? ? ? ? ? 0.008 ? + 1.7 ( ) 24v ( ) 3 4a 12v 150pf ( ) 350khz ( ) = 0.7w c out is chosen to filter the square current in the output. the maximum output current peak is: i out(peak) = i out(max) ? 1+ ripple% 2 ? ? ? ? ? ? = 4 ? 1+ 31% 2 ? ? ? ? ? ? = 4.62a a low esr (5m) capacitor is suggested. this capacitor will limit output voltage ripple to 23.1mv (assuming esr dominate ripple). pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 6. figure 7 illustrates the current waveforms present in the various branches the synchro- nous regulator operating in the continuous mode. check the following in your layout: 1. put the bottom n-channel mosfet mbot and the top n-channel mosfet mtop in one compact area with c out . 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the bottom n-channel mosfet and the capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) source terminal of the bottom mosfet. 3. does the ltc3786 vfb pin s resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground and placed close to the vfb pin. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pin? this capacitor carries the mosfet drivers cur - rent peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and gnd pins can help improve noise performance substantially. 6. keep the switching node (sw), top gate node (tg) and boost node (boost) away from sensitive small-signal nodes. all of these nodes have very large and fast moving signals and, therefore, should be kept on the output side of the ltc3786 and occupy a minimal pc trace area. 7. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the int v cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic.
ltc3786 23 3786fa a pplica t ions i n f or m a t ion pc board layout debugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. moni - tor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main- tained over the input voltage range down to dropout and until the output load drops below the low current opera- tion threshold typically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pick-up at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation with high duty cycle. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. an embarrassing problem, which can be missed in an otherwise properly working switching regulator results when the current sensing leads are hooked up backwards. the output voltage under this improper hook-up will still be maintained, but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage.
ltc3786 24 3786fa a pplica t ions i n f or m a t ion sense + sense ? pgood v pullup v in v out sw tg boost bg f in c b m1 m2 gnd 3786 f06 l1 r sense vbias gnd ltc3786 freq pllin/mode run vfb ith ss intv cc + + r l l1 sw r sense v out c out 3786 f07 v in c in r in bold lines indicate high switching current. keep lines to a minimum length figure 6. recommended printed circuit layout diagram figure 7. branch current waveforms
ltc3786 25 3786fa a pplica t ions i n f or m a t ion sense + sense ? tg c b 0.1f c itha 220pf ltc3786 c ss 0.1f c ith 15nf c in 22f mtop mbot d c int 4.7f 3786 f08 v out 24v 5a* v in 5v to 24v r sense 4m l 3.3h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.66k r s 232k c in , c outa : tdk c4532x5r1e226m c outb : sanyo 50ce220lx d: bas140w l: pulse pa1494.362nl mbot, mtop: renesas hat2169h *when v in < 8v, maximum load current available is reduced. freq run pllin/mode c outa 22f 4 c outb 220f + figure 8. high efficiency 24v boost converter figure 9. high efficiency 28v boost converter sense + sense ? tg c b 0.1f c itha 220pf ltc3786 c ss 0.1f c ith 15nf c in 6.8f 4 mtop mbot d c int 4.7f 3786 f09 v out 28v 4a* v in 5v to 28v r sense 4m l 3.3h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.66k r s 261k freq run pllin/mode c outa 6.8f 4 c outb 220f + c in , c outa : tdk c4532x7r1h685k c outb : sanyo 63ce220kx d: bas140w l: pulse pa1494.362nl mbot, mtop: renesas hat2169h *when v in < 8v, maximum load current available is reduced.
ltc3786 26 3786fa a pplica t ions i n f or m a t ion figure 10. high efficiency 36v boost converter figure 11. 10.5v nonsynchronous sepic converter sense + sense ? tg c b 0.1f c itha 220pf ltc3786 c ss 0.1f c ith 15nf c in 6.8f 4 mtop mbot d c int 4.7f 3786 f10 v out 36v 3a* v in 5v to 36v r sense 5m l 10.2h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.66k r s 357k freq run pllin/mode c outa 6.8f 4 c outb 220f + c in , c outa : tdk c4532x7r1h685k c outb : sanyo 63ce220kx d: bas170w l: pulse pa2050.103nl mbot, mtop: renesas rjic0652dpb *when v in < 9v, maximum load current available is reduced. sense + sense ? tg c itha 10pf ltc3786 c ss 0.1f c ith 100nf c in 22f mbot c int 4.7f 3786 f11 v out 10.5v 1.2a v in 5.8v to 34v r sense 9m l 10h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 115k 100k r ith 13k r s 887k freq run pllin/mode c out 270f d c 10f ? ? c in : sanyo 50ce220lx c out : sanyo svpc270m d: diodes, inc. b360a-13-f l: cooper bussmann drq125-100 mbot: bsz097no4l
ltc3786 27 3786fa a pplica t ions i n f or m a t ion figure 12. high efficiency 10v boost converter output current (a) 321 94 efficiency (%) 96 98 4 5 6 3786 f12b 92 90 88 86 100 v in = 12v v in = 9v v in = 6v sense + sense ? tg c b 0.1f c itha 100pf ltc3786 c ss 0.1f c ith 10nf c in 22f mbot mtop d c int 4.7f 3786 f12a v out * 10v 5a v in 4.5v to 24v start-up voltage operates through transients down to 2.5v l 3.2h boost sw vbias bg gnd pllin/mode pgood intv cc vfb ith ss r a 12.1k 100k 100k r ith 4.64k 60.4k f sw = 400khz r b 88.7k freq run c outa 22f 3 r sense 5m c outb 150f + c in , c outa : tdk c4532x5r1e226m c outb : sanyo 35hvh150m l: sumida cdep106-3r2-88 mbot, mtop: renesas hat2170 d: infineon bas140w *when v in > 10v, v out follows v in .
ltc3786 28 3786fa a pplica t ions i n f or m a t ion figure 13. low i q lithium-ion to 5v/4a boost converter sense + sense ? tg c b 0.1f c itha 100pf ltc3786 c ss 0.1f c ith 6.8nf c in 47f 2 mtop mbot d1 3786 f13a v out 5v 4a v in 2.7v to 4.2v c1 10f c f ly 1f r sense 6m l 0.67h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 150k 100k r ith 5.11k r b 475k freq run pllin/mode c out 47f 4 v out ltc1754-5 c + c ? v in shdn gnd c in , c out : tdk c3225x5r1a476m l: toko fdv0840-r67m mbot, mtop: infineon bsc046n02ks q: vishay siliconix si1499dh d1: infineon bas140w d2: nxp pmeg2005ej c f ly : murata grm39x5r105k6.3aj c1, c2: murata grm40x5r106k6.3aj c int 4.7f d2 q 1m c2 10f output current (a) 3 2 1 0 94 efficiency (%) 96 4 3786 f13b 92 90 88 86 98 v in = 4.2v v in = 3.3v v in = 2.7v
ltc3786 29 3786fa a pplica t ions i n f or m a t ion figure 14. high efficiency 24v boost converter with inductor dcr current sensing output current (a) 3 2 1 0 94 efficiency (%) 96 4 3786 f14b 92 90 88 86 100 98 v in = 12v sense + sense ? tg c itha 220pf c b 0.1f ltc3786 c ss 0.1f c ith 15nf c in 22f mbot mtop d c int 4.7f 3786 f14a v out 24v 4a v in 5v to 24v r s2 26.1k 1% c1 0.1f l 10.2h boost sw vbias bg gnd pllin/mode pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.87k r b 232k freq run c outa 22f 4 c outb 220f + c1: tdk c1005x7r1c104k c in , c outa : tdk c4532x5r1e226m c outb : sanyo, 50ce220ax l: pulse pa2050.103nl mbot, mtop: renesas rjk0305 d: infineon bas140w r s1 53.6k 1%
ltc3786 30 3786fa a pplica t ions i n f or m a t ion figure 15. low i q high voltage flyback power supply sense + sense ? tg c itha 100pf ltc3786 c ss 0.1f c ith 22nf c in 22f 2 mbot c int 4.7f 3786 f15 v out 350v 10ma v in 5v to 12v 10nf r sense 15m boost sw vbias bg gnd pgood intv cc vfb ith ss 16.2k 1% 1m 1% 1m 1% 1.5m 1% 100k 22 220pf r ith 8.66k 25k f sw = 105khz freq run pllin/mode c out 68nf 2 d t 1:10 c in : tdk c3225x7r1c226m c out : tdk c3225x7r2j683k d: vishay siliconix gsd2004s dual diode connected in series mbot: vishay siliconix si7850dp t: tdk dct15efd-u44s003 danger high voltage! operation by high voltage trained personnel only ? ? figure 16. low i q nonsynchronous 24v/2a boost converter sense + sense ? tg c itha 100pf ltc3786 c ss 0.1f c ith 22nf c in 10f 2 mbot d c int 4.7f 3786 f15 v out 24v 2a v in 5v to 24v r sense 6m l 10h boost sw vbias bg gnd pgood intv cc vfb ith ss 12.1k 1% 100k r ith 8.66k 232k 1% freq run pllin/mode c outa 10f c outb 47f 4 + c in , c outa : murata grm31cr61e106ka12 c outb : kemet t495x476k035as d: on semi mbrs340t3g l: visay siliconix ihlp-5050fd-01 10h mbot: vishay siliconix si4840bdp
ltc3786 31 3786fa p ackage descrip t ion mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev c) msop (mse16) 0910 rev c 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3786 32 3786fa p ackage descrip t ion ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3786 33 3786fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 9/11 updated the topside mosfet driver supply (c b , d b ) section. updated figure 12. 18 27
ltc3786 34 3786fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0911 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion high efficiency 48v boost converter sense + sense ? tg c b 0.1f c itha 220pf ltc3786 c ss 0.1f c ith 15nf c in 6.8f 4 mtop mbot d c int 4.7f 3786 ta02 v out 48v 2a* v in 5v to 38v r sense 8m l 16h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.66k r s 475k freq run pllin/mode c outa 6.8f 4 c outb 220f + c in , c outa : tdk c4532x7r1h685k c outb : sanyo 63ce220kx d: bas170w l: pulse pa2050.163nl mbot, mtop: renesas rjk0652dpb *when v in < 13v, maximum load current available is reduced. part number description comments ltc3788/ltc3788-1 2-phase dual output synchronous step-up controllers 4.5v v in 38v, v out up to 60v, 50khz to 900khz, 5mm w 5mm qfn-32 and ssop-28 packages ltc3787 2-phase single output synchronous boost controller 4.5v v in 38v, v out up to 60v, 50khz to 900khz, 5mm w 5mm qfn-28 and ssop-28 packages ltc3859 low i q , triple output, buck/buck/boost synchronous controller 4.5v v in 38v, boost output voltage up to 60v, 50khz to 900khz, 5mm w 7mm qfn-38 and tssop-38 packages ltc3862/ltc3862-1 multiphase current mode step-up dc/dc controllers 4v v in 36v, 5v or 10v gate drive, 75khz to 500khz, ssop-24, tssop-24, 5mm w 5mm qfn-24 ltc3813/ltc3814-5 100v/60v maximum v out current mode synchronous step-up dc/dc controllers no r sense , large 1 gate driver, adjustable off-time, ssop-28, tssop-16 ltc1871, ltc1871-1, ltc1871-7 wide input range, no r sense ? low quiescent current flyback, boost and sepic controllers adjustable switching frequency, 2.5v v in 36v, burst mode operation at light load, msop-10 lt ? 3757/lt3758 boost, flyback, sepic and inverting controllers v in up to 40v/100v, 100khz to 1mhz programmable operation frequency, 3mm w 3mm dfn-10 and msop-10e ltc3780 high efficiency synchronous 4-switch buck-boost dc/ dc controller 4v v in 36v, 0.8v v out 30v, ssop-24, 5mm w 5mm qfn-32

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